Programmable platform architectures for Very Large Scale Integrated (VLSI) circuit designs provide a fixed set of resources for implementing different custom logic designs applied to the platform. Embedded memory is one such resource. The embedded memory requirements of different custom logic designs to be applied to the same programmable platform device can be quite different.
In conventional solutions, standard size embedded memory blocks are provided by the programmable platform device. The blocks are combined to create a desired memory width and depth. The conventional solutions suffer from a lack of flexibility. The designer of the circuit to be fabricated on the programmable platform device has very little flexibility in the customized use of the embedded arrays. The chip designer can only use the resources provided in the restricted mode that has been implemented by the platform designer. A situation can occur where the chip designer does not have the resources to use a memory in an organization best suited to the application.
Conventional solutions also waste die real estate. Combining embedded memory arrays of a preset size can lead to wasted die area. For example, creating a 256×50 array by combining two available 256×40 arrays wastes 75% of the second array. Conventional solutions can also result in late timing information feedback. The effect of the interconnection delay on the timing of the random access memory is not discovered until full chip timing tests can be made, which is usually late in the design process. When working to minimize the time to design a custom logic chip, the earlier in the process that accurate design constraints can be provided to the designer, the simpler (and quicker) relevant design tradeoffs between choices can be made. When accurate information is available only later in the process, significant rework can be necessary, essentially restarting the design with new constraint information, thus negating the progress made under the inaccurate assumptions.
It would be desirable to provide an embedded memory solution that may fulfill the memory size and performance specifications of different designs using a fixed set of resources.